FPGA实现SPI通讯协议（Verilog）

[{"title":"（ 149 个子文件 4.33MB ） FPGA实现SPI通讯协议（Verilog）","children":[{"title":"SPI_MasterToSlave_tb.v <span style='color:#111;'> 636B </span>","children":null,"spread":false},{"title":"SPI_MasterToSlave_tb.v.bak <span style='color:#111;'> 661B </span>","children":null,"spread":false},{"title":"SlaveGetMaster.v <span style='color:#111;'> 1.43KB </span>","children":null,"spread":false},{"title":"SPI_MasterToSlave.v.bak <span style='color:#111;'> 3.35KB </span>","children":null,"spread":false},{"title":"SlaveGetMaster.v.bak <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]