architecture behav of codesdect is
signal m : integer range 0 to 3;
signal sdata : std_logic_vector(2 downto 0);
begin
cdata<= wavenum;
process(clk,clr)
begin
if clr='1' then m if datain = cdata (2) then m<=1; else m if datain = cdata (0) then m<=3; else m m <= 0;
2021-04-13 16:40:01
275KB
FPGA
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