操作系统课程FiFO，OPT，LRU三种页面置换算法用C++实现，代码清晰，有少量注释，希望给有上机的孩子们一些参考

使用verilog开发的带fifo的串口，波特率115200,8,n,1，已在fpga上验证通过。

将 linux 内核的 kfifo 移植到应用层, 实现一种易使用, 高效率的 fifo 队列

博客配套源码工程 https://blog.csdn.net/botao_li/article/details/95302992

xilinx的FIFO_generator的ip核详述，提供了各个管脚的功能，以及例化模板

TI DSP 28335 串口FIFO中断接收程序 打开后在工程添加文件中的comm_2int_fifo.c文件即可。 该文件已经本人调试成功可用。

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.

一个页面置换算法性能比较程序，包括了最佳置换，先进先出，LRU，随机置换，简单时钟和改进时钟六个算法。使用了队列，链表，循环链表等数据结构。随机产生请求页号，计算六种算法的缺页率。

xilinx 官方fifo IP使用手册，里面描述了关于xilinx官方IP FIFO的所有使用细节

实现OPT、LRU、FIFO以及Clock四种不同的页面置换策略，界面良好