基于verilog的带fifo的串口设计

[{"title":"（ 628 个子文件 17.03MB ） 基于verilog的带fifo的串口设计","children":[{"title":"pin.tcl <span style='color:#111;'> 329B </span>","children":null,"spread":false},{"title":"tx_fifo.qip <span style='color:#111;'> 450B </span>","children":null,"spread":false},{"title":"my_uart_tx.v.bak <span style='color:#111;'> 3.37KB </span>","children":null,"spread":false},{"title":"uart_test_top.v <span style='color:#111;'> 3.25KB </span>","children":null,"spread":false},{"title":"ram_buf.v <span style='color:#111;'> 5.44KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]