用vivado编写的数字钟实验代码文件，功能包括时钟，闹钟，正计时，倒计时等功能，亲测可以在basys3板子上跑起来，代码上有错误不可避免，希望这些代码能够在大家完成数字钟实验的时候帮助到大家，起到一个参考的作用

绿皮书

systemverilog-python Systemverilog DPI-C调用Python函数 0.systemverilog_only python3 -m pip install scapy cd 0.systemverilog_only export PYTHONPATH=. make 日志 \rm -rf simv* csrc* *.log __pycache__ ucli.key vc_hdrs.h stack.info.* vcs -full64 -LDFLAGS -Wl,--no-as-needed +incdir+./c -CC -lpython3.6m -CC -lpthread -CC -ldl -CC -lutil -lm -LDFLAGS -lpython3.6m -CC -I/usr/include/python3.6m -

golden reference guide of system Verilog

SystemVerilog IEEE 1800-2017.pdf SystemVerilog IEEE 1800-2017.pdf SystemVerilog IEEE 1800-2017.pdf

在verilog.clf的基础上作了一些增强，支持了部分常用的systemverilog语法

IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language

This book has one large omission: assertions and formal verification. It is not that they are not important. SystemVerilog includes constructs and semantics for writing assertions and coverage properties using temporal expressions. Formal verification is already an effective methodology for verifying certain classes of designs. It is simply a matter of drawing a line somewhere. There are already books on assertions1 or formal verification. This book focuses on the bread-and-butter of verification for the foreseeable future: dynamic functional verification using testbenches 以下的资源也很不错, 加减可以看一下o 使用C++制作3D动画人物-100%提供源码 http://download.csdn.net/source/2255453 http://hqioan.download.csdn.net/

Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny (auth.) - SVA_ The Power of Assertions in SystemVerilog-Springer International Publishing (2015)

verilog-fp 浮点协处理器（Verilog）