PWM波实验FPGA设计Verilog逻辑源码Quartus11.0工程文件,FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module pwm(clk,reset,key,led);
input clk,reset,key;
output led;
reg pwm_out;
reg key_out;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
reg [1:0] state;
reg [31:0] clk_counter;
reg [9:0] pwm_counter;
reg flag;
/******************按键消抖**************************/
always @(posedge clk)
begin
case (state)
s0:
begin
key_out<=1'b1;
if(key==1'b0)
state<=s1;
else
state<=s0;
end
s1:
begin
if(key==1'b0)
state<=s2;
else
state<=s0;
end
s2:
begin
if(key==1'b0)
state<=s3;
else
state<=s0;
end
s3:
begin
if(key==1'b0)
begin
key_out<=1'b0;
state<=s3;
end
else
begin
key_out<=1'b1;
state<=s0;
end
end
default:
state<=s0;
endcase
end
always @(posedge clk)
begin
clk_counter<=clk_counter+1'b1;
if (clk_counter[13:4]
2021-08-23 13:07:37
3.01MB