FPGA 读写SRAM存储verilog设计实验Quartus9.1工程源码+设计说明文件，可以做为你的学习设计参考。 module sram_test( clk,rst_n,led, sram_addr,sram_wr_n,sram_data ); input clk; // 50MHz input rst_n; //低电平复位 output led; // LED1 // FPGA与SRAM外部接口 output[17:0] sram_addr; // SRAM地址总线 output sram_wr_n; // SRAM写选通 inout[15:0] sram_data; // SRAM数据总线 //------------------------------------------------------- reg[25:0] delay; //延时计数器 always @ (posedge clk or negedge rst_n) if(!rst_n) delay <= 26'd0; else delay <= delay+1; //不断计数，周期约为1.28s //------------------------------------------------------- reg[15:0] wr_data; // SRAM写入数据总线 reg[15:0] rd_data; // SRAM读出数据 reg[17:0] addr_r; // SRAM地址总线 wire sram_wr_req; // SRAM写请求信号 wire sram_rd_req; // SRAM读请求信号 reg led_r; // LED寄存器 assign sram_wr_req = (delay == 26'd9999); //产生写请求信号 assign sram_rd_req = (delay == 26'd19999); //产生读请求信号 always @ (posedge clk or negedge rst_n) if(!rst_n) wr_data <= 16'd0; else if(delay == 26'd29999) wr_data <= wr_data+1'b1; //写入数据每1.28s自增1 always @ (posedge clk or negedge rst_n) if(!rst_n) addr_r <= 18'd0; else if(delay == 26'd29999) addr_r <= addr_r+1'b1; //写入地址每1.28s自增1 always @ (posedge clk or negedge rst_n) if(!rst_n) led_r <= 1'b0; else if(delay == 26'd20099) begin //每1.28s比较一次同一地址写入和读出的数据 if(wr_data == rd_data) led_r <= 1'b1; //写入和读出数据一致，LED点亮 else led_r <= 1'b0; //写入和读出数据不同，LED熄灭 end assign led = led_r; //------------------------------------------------------- `define DELAY_80NS (cnt==3'd7) reg[2:0] cnt; //延时计数器 always @ (posedge clk or negedge rst_n) if(!rst_n) cnt <= 3'd0; else if(cstate == IDLE) cnt <= 3'd0; else cnt <= cnt+1'b1; //------------------------------------ parameter IDLE = 4'd0, WRT0 = 4'd1, WRT1 = 4'd2, REA0 = 4'd3, REA1 = 4'd4; reg[3:0] cstate,nstate; always @ (posedge clk or negedge rst_n) if(!rst_n) cstate <= IDLE; else cstate <= nstate; always @ (cstate or sram_wr_req or sram_rd_req or cnt) case (cstate) IDLE: if(sram_wr_req) nstate <= WRT0

Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件 module SRAM_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] SRAM_DQ , output reg [17:0] SRAM_ADDR , output reg SRAM_CE , output reg SRAM_OE , output reg SRAM_WE , output reg SRAM_UB , output reg SRAM_LB , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg sram_clk ; reg [5:0] ctrl_cnt ; reg [15:0] sram_data_lck ; reg [15:0] sram_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to sram ctrl clk 50M/16 always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen sram_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) sram_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) sram_clk <= 1'b1 ; else sram_clk <= 1'b0 ; end // sram ctrl signal gen // ctrl_cnt 0 - 31 is for write ctrl // ctrl_cnt 31 - 63 is for read ctrl always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 6'b0; else ctrl_cnt <= ctrl_cnt + 6'b1; end always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) SRAM_ADDR <= 18'b0; else if ( ctrl_cnt