LCD1602显示屏显示字符实验FPGA设计Verilog逻辑源码Quartus11.0工程文件，FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module my1602(clk,RS,RW,E,Data,back_light);
input clk; //50MHZ时钟的输入
output RS,RW,E; //1602的控制信号使能，数据/命令，读/写
output [7:0]Data; //数据端
output back_light; //背光
reg RS;
reg [7:0]Data;
parameter address=8'h80; //第一行
parameter address2=8'hc0; //第二行
assign RW=1'b0; //只用显示时，一直是写的状态
assign back_light=1'b1; //背光灯打开
reg clk_e;
reg [15:0]count;
always @(posedge clk)
begin
count=count+1'b1;
if(count==16'hf000)
begin
clk_e=~clk_e; //作为使能端
count=16'd0;
end
end
reg [1:0]jishu;
reg [4:0]zhuangtai; //状态机状态
reg temp;
always @(posedge clk_e)
begin
case(zhuangtai)
5'b00000:begin
temp<=1'b0;
RS<=1'b0;
Data<=8'h38;//显示模式设置
zhuangtai<=zhuangtai+1'b1;
end
5'b00001:begin
RS<=1'b0;
Data<=8'h0c;//显示开及光标设置
zhuangtai<=zhuangtai+1'b1;
end
5'b00010:begin
RS<=1'b0;
Data<=8'h06;//显示光标移动设置
zhuangtai<=zhuangtai+1'b1;
end
5'b00011:begin
RS<=1'b0;
Data<=8'h01;//显示
2021-08-23 13:13:57
3.22MB
PWM波实验FPGA设计Verilog逻辑源码Quartus11.0工程文件,FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module pwm(clk,reset,key,led);
input clk,reset,key;
output led;
reg pwm_out;
reg key_out;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
reg [1:0] state;
reg [31:0] clk_counter;
reg [9:0] pwm_counter;
reg flag;
/******************按键消抖**************************/
always @(posedge clk)
begin
case (state)
s0:
begin
key_out<=1'b1;
if(key==1'b0)
state<=s1;
else
state<=s0;
end
s1:
begin
if(key==1'b0)
state<=s2;
else
state<=s0;
end
s2:
begin
if(key==1'b0)
state<=s3;
else
state<=s0;
end
s3:
begin
if(key==1'b0)
begin
key_out<=1'b0;
state<=s3;
end
else
begin
key_out<=1'b1;
state<=s0;
end
end
default:
state<=s0;
endcase
end
always @(posedge clk)
begin
clk_counter<=clk_counter+1'b1;
if (clk_counter[13:4]
2021-08-23 13:07:37
3.01MB