按键消抖实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料，FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module key_debounce( input clk, input rst_n, input key, output [3:0] led ); wire button_negedge; //Key falling edge ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key), .button_posedge (), .button_negedge (button_negedge), .button_out () ); wire[3:0] count; wire t0; count_m10 count10_m0( .clk (clk), .rst_n (rst_n), .en (button_negedge), .clr (1'b0), .data (count), .t (t0) ); assign led = ~count; endmodule