Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料,, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module spi_flash_top( input sys_clk, input rst, output nCS, output DCLK, output MOSI, input MISO, input[15:0] clk_div, input[3:0] cmd, input cmd_valid, output cmd_ack, input[23:0] addr, input[7:0] data_in, input[8:0] size, output data_req, output reg[7:0] data_out, output reg data_valid ); localparam S_IDLE = 0; localparam S_SE = 1; localparam S_BE = 2; localparam S_READ = 3; localparam S_WRITE = 4; localparam S_ACK = 5; localparam S_CK_STATE = 6; //present state monitor localparam S_WREN = 7; wire spi_flash_cmd_ack; reg[3:0] sub_cmd; reg sub_cmd_valid; reg[8:0] sub_size; reg[4:0] state,next_state; reg[7:0] state_reg; wire sub_data_valid; wire[7:0] sub_data_in; wire[7:0] sub_data_out; assign sub_data_in = data_in; assign cmd_ack = (state == S_ACK); always@(posedge sys_clk or posedge rst) begin if(rst==1) state <= S_IDLE; else state <= next_state; end always@(*) begin case(state) S_IDLE: if(cmd_valid && cmd == `CMD_BE) next_state <= S_WREN; else if(cmd_valid && cmd == `CMD_SE) next_state <= S_WREN; else if(cmd_valid && cmd == `CMD_READ) next_state <= S_READ; else if(cmd_valid && cmd == `CMD_PP) next_state <= S_WREN; else next_state <= S_IDLE; S_WREN: if(spi_flash_cmd_ack && cmd == `CMD_BE) next_state <= S_BE; else if(spi_flash_cmd_ack && cmd == `CMD_SE) next_state <= S_SE; else if(spi_flash_cmd_ack && cmd == `CMD_PP) next_state <= S_WRITE; else next_state <= S_WREN; S_BE: if(spi_flash_cmd_ack) next_state <= S_CK_STATE;//读取状态寄存器 else next_state <= S_BE; S_SE: if(spi_flash_cmd_ack) next_state <= S_CK_STATE;

Cyclone10 FPGA读写eeprom(24lc04)实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module i2c_master_top ( input rst, input clk, input[15:0] clk_div_cnt, // I2C signals // i2c clock line input scl_pad_i, // SCL-line input output scl_pad_o, // SCL-line output(always 1'b0) output scl_padoen_o, // SCL-line output enable(active low) // i2c data line input sda_pad_i, // SDA-line input output sda_pad_o, // SDA-line output (always 1'b0) output sda_padoen_o, // SDA-line output enable (active low) input i2c_addr_2byte, input i2c_read_req, output i2c_read_req_ack, input i2c_write_req, output i2c_write_req_ack, input[7:0] i2c_slave_dev_addr, //device address input[15:0]i2c_slave_reg_addr, //word address input[7:0] i2c_write_data, output reg[7:0]i2c_read_data, output reg error ); localparam S_IDLE = 0; localparam S_WR_DEV_ADDR = 1; localparam S_WR_REG_ADDR = 2; localparam S_WR_DATA = 3; localparam S_WR_ACK = 4; localparam S_WR_ERR_NACK = 5; localparam S_RD_DEV_ADDR0 = 6; localparam S_RD_REG_ADDR = 7; localparam S_RD_DEV_ADDR1 = 8; localparam S_RD_DATA = 9; localparam S_RD_STOP = 10; localparam S_WR_STOP = 11; localparam S_WAIT = 12; localparam S_WR_REG_ADDR1 = 13; localparam S_RD_REG_ADDR1 = 14; localparam S_RD_ACK = 15; reg start; reg stop; reg read; reg write; reg ack_in; reg[7:0] txr; wire[7:0] rxr; wire i2c_busy; //It was high level after start signal and low level after stop signal wire i2c_al; //arbitrament lose(The stop signal is detected but no signal is requested.The host setting SDA is high,Actual SDA is low) wire done; wire irxack; //slave receive the respond，0 (receive)，1(refuse) reg[3:0] state,next_state; assign i2c_read

Uart串口读写实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module uart_test( input clk, input rst_n, input uart_rx, output uart_tx ); parameter CLK_FRE = 50;//Mhz localparam IDLE = 0; localparam SEND = 1; //send HELLO ALINX\r\n localparam WAIT = 2; //wait 1 second and send uart received data reg[7:0] tx_data; reg[7:0] tx_str; reg tx_data_valid; wire tx_data_ready; reg[7:0] tx_cnt; wire[7:0] rx_data; wire rx_data_valid; wire rx_data_ready; reg[31:0] wait_cnt; reg[3:0] state; assign rx_data_ready = 1'b1;//always can receive data, //if HELLO ALINX\r\n is being sent, the received data is discarded always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin wait_cnt <= 32'd0; tx_data <= 8'd0; state <= IDLE; tx_cnt <= 8'd0; tx_data_valid <= 1'b0; end else case(state) IDLE: state <= SEND; SEND: begin wait_cnt <= 32'd0; tx_data <= tx_str; if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < 8'd12)//Send 12 bytes data begin tx_cnt <= tx_cnt + 8'd1; //Send data counter end else if(tx_data_valid && tx_data_ready)//last byte sent is complete begin tx_cnt <= 8'd0; tx_data_valid <= 1'b0; state <= WAIT; end else if(~tx_data_valid) begin tx_data_valid <= 1'b1; end end WAIT: begin wait_cnt <= wait_cnt + 32'd1; if(rx_data_valid == 1'b1) begin tx_data_valid <= 1'b1; tx_data <= rx_data; // send uart received data end else if(tx_data_valid && tx_da

按键消抖实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料，FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module key_debounce( input clk, input rst_n, input key, output [3:0] led ); wire button_negedge; //Key falling edge ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key), .button_posedge (), .button_negedge (button_negedge), .button_out () ); wire[3:0] count; wire t0; count_m10 count10_m0( .clk (clk), .rst_n (rst_n), .en (button_negedge), .clr (1'b0), .data (count), .t (t0) ); assign led = ~count; endmodule

sdram读写测试实验Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料,FPGA为CYCLONE10LP系列中的10CL025YU256C8.SDRAMN HYNIX/海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的 TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,完整的Quartus工程文件，可以做为你的学习设计参考。 module top ( input clk, input rst_n, output[1:0] led, output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16 ; //external memory user interface data width parameter ADDR_BITS = 24 ; //external memory user interface address width parameter BUSRT_BITS = 10 ; //external memory user interface burst width parameter BURST_SIZE = 128 ; //burst size wire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clock wire wr_burst_finish; // from external memory controller,burst write finish wire rd_burst_finish; // from external memory controller,burst read finish wire rd_burst_req; // to external memory controller,send out a burst read request wire wr_burst_req; // to external memory controller,send out a burst write request wire[BUSRT_BITS - 1:0] rd_burst_len; // to exter

USB2.0测速实验Cyclone10 FPGA Verilog源码Quartus17.1工程文件+文档资料，FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module top ( input clk, input ft_clk, input ft_rxf_n, //Data available input ft_txe_n, //Space available output ft_oe_n, output ft_rd_n, output ft_wr_n, inout[7:0] ft_data ); ft232h ft232h_m0 ( .ft_clk (ft_clk ), .rst (1'b0 ), .ft_rxf_n (ft_rxf_n), //Data available .ft_txe_n (ft_txe_n), //Space available .ft_oe_n (ft_oe_n ), .ft_rd_n (ft_rd_n ), .ft_wr_n (ft_wr_n ), .ft_data (ft_data ) ); module ft232h ( input ft_clk, input rst, input ft_rxf_n, //Data available input ft_txe_n, //Space available output ft_oe_n, output reg ft_rd_n, output ft_wr_n, inout[7:0] ft_data ); localparam IDLE = 0; localparam READ = 1; localparam WRITE = 2; reg[3:0] state; reg buf_wr; reg[7:0] buf_data; wire[7:0] ft_data_out; wire buf_empty; wire buf_full; wire buf_rd; reg ft_oe_n_d0; assign ft_oe_n = (state == READ) ? 1'b0 : 1'b1; assign ft_data = (ft_oe_n == 1'b0) ? 8'hzz : ft_data_out; assign ft_wr_n = (state == WRITE && ft_txe_n == 1'b0 && buf_empty == 1'b0) ? 1'b0 : 1'b1; assign buf_rd = (state == WRITE && ft_txe_n == 1'b0 && buf_empty == 1'b0) ? 1'b1 : 1'b0; ft_buf ft_buf_m0( .aclr (1'b0 ), .data (buf_data ), .rdclk (ft_clk ), .rdreq (buf_rd ), .wrclk (ft_clk ), .wrreq (buf_wr ), .q (ft_data_out ),