附件有详细的设计规格书。Features - Compatible with Motorola's SPI specifications - Enhanced Motorola MC68HC11 Serial Peripheral Interface - 4 entries deep read FIFO - 4 entries deep write FIFO - Interrupt generation after 1, 2, 3, or 4 transfered bytes - 8 bit WISHBONE RevB.3 Classic interface - Operates from a wide range of input clock frequencies - Static synchronous design - Fully synthesizable - 130LUTs in a Spartan-II, 230 LCELLs in an ACEX
2021-09-15 20:23:18 42KB 完全可综合 SPI模块 verilog 代码
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