基于Vivado2018的16QAM调制完整工程文件，采用全verilog语言，可直接testbench仿真

[{"title":"（ 181 个子文件 58.1MB ） 基于Vivado2018的16QAM调制完整工程文件，采用全verilog语言，可直接testbench仿真","children":[{"title":"cnn_tb_vhdl.prj <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"cordic_tb.tcl <span style='color:#111;'> 460B </span>","children":null,"spread":false},{"title":"top_sim_behav.wdb <span style='color:#111;'> 24.40KB </span>","children":null,"spread":false},{"title":"testbench.tcl <span style='color:#111;'> 460B </span>","children":null,"spread":false},{"title":"tb_TOP_vlog.prj <span style='color:#111;'> 307B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]