上传者: zongfabao
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上传时间: 2022-05-15 20:01:20
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文件大小: 8KB
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文件类型: TXT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgacore is
Port ( clk : in std_logic;
reset : in std_logic;
md : in std_logic_vector(1 downto 0);
hs : out std_logic;
vs : out std_logic;
r : out std_logic_vector(1 downto 0);
g : out std_logic_vector(2 downto 0);
b : out std_logic_vector(2 downto 0)
);
end vgacore;