SDRAM控制器 能够时序仿真

[{"title":"（ 54 个子文件 1.19MB ） SDRAM控制器 能够时序仿真","children":[{"title":"sdram","children":[{"title":"transcript <span style='color:#111;'> 503B </span>","children":null,"spread":false},{"title":"ddr_control_interface.v <span style='color:#111;'> 7.12KB </span>","children":null,"spread":false},{"title":"note.txt <span style='color:#111;'> 82B </span>","children":null,"spread":false},{"title":"ddr_sdram_tb.v <span style='color:#111;'> 14.71KB </span>","children":null,"spread":false},{"title":"Params.v <span style='color:#111;'> 311B </span>","children":null,"spread":false},{"title":"pll1.v <span style='color:#111;'> 989B </span>","children":null,"spread":false},{"title":"ddr.mpf <span style='color:#111;'> 19.13KB </span>","children":null,"spread":false},{"title":"ddr.cr.mti <span style='color:#111;'> 2.53KB </span>","children":null,"spread":false},{"title":"chart","children":[{"title":"图9-26.bmp <span style='color:#111;'> 530.44KB </span>","children":null,"spread":false},{"title":"图9-16.bmp <span style='color:#111;'> 487.67KB </span>","children":null,"spread":false},{"title":"图9-20.bmp <span style='color:#111;'> 518.47KB </span>","children":null,"spread":false},{"title":"图9-22.bmp <span style='color:#111;'> 573.22KB </span>","children":null,"spread":false},{"title":"图9-23.bmp <span style='color:#111;'> 465.43KB </span>","children":null,"spread":false},{"title":"图9-27.bmp <span style='color:#111;'> 530.44KB </span>","children":null,"spread":false},{"title":"图9-17.bmp <span style='color:#111;'> 527.02KB </span>","children":null,"spread":false},{"title":"图9-19.bmp <span style='color:#111;'> 501.29KB </span>","children":null,"spread":false},{"title":"Thumbs.db <span style='color:#111;'> 25.50KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_data_path.v <span style='color:#111;'> 7.42KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 1.18MB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"mt46v4m16","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 244.17KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 24.52KB </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"ddr_command","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 39.68KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 5.01KB </span>","children":null,"spread":false}],"spread":false},{"title":"ddr_control_interface","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 21.15KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false}],"spread":false},{"title":"pll1","children":[{"title":"_primary.vhd <span style='color:#111;'> 256B </span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'> 524B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 5.45KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 823B </span>","children":null,"spread":false}],"spread":false},{"title":"ddr_sdram_tb","children":[{"title":"_primary.vhd <span style='color:#111;'> 84B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 63.93KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 9.18KB </span>","children":null,"spread":false}],"spread":false},{"title":"ddr_data_path","children":[{"title":"_primary.vhd <span style='color:#111;'> 817B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 20.14KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.10KB </span>","children":null,"spread":false}],"spread":false},{"title":"ddr_sdram","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 29.30KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 4.45KB </span>","children":null,"spread":false}],"spread":false},{"title":"altclklock","children":[{"title":"_primary.vhd <span style='color:#111;'> 899B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 22.50KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.28KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"ddr_Command.v <span style='color:#111;'> 13.18KB </span>","children":null,"spread":false},{"title":"ddr_sdram.v <span style='color:#111;'> 7.52KB </span>","children":null,"spread":false},{"title":"wave","children":[{"title":"ddr_control_interface.bmp <span style='color:#111;'> 1.93MB </span>","children":null,"spread":false},{"title":"ddr_command.bmp <span style='color:#111;'> 2.36MB </span>","children":null,"spread":false},{"title":"ddr_data_path.bmp <span style='color:#111;'> 2.36MB </span>","children":null,"spread":false},{"title":"ddr_sdram_tb.bmp <span style='color:#111;'> 2.09MB </span>","children":null,"spread":false},{"title":"ddr_sdram.bmp <span style='color:#111;'> 2.36MB </span>","children":null,"spread":false},{"title":"Thumbs.db <span style='color:#111;'> 18.50KB </span>","children":null,"spread":false}],"spread":false},{"title":"altclklock.v <span style='color:#111;'> 3.55KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]