[{"title":"( 1057 个子文件 13.48MB ) Verilog HDL程序设计实例详解 配套光盘","children":[{"title":"_info <span style='color:#111;'> 2.76KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 2.24KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 2.02KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.84KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.83KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.65KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.61KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.56KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.16KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.07KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 907B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 839B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 569B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 420B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 416B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 412B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 412B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 394B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 392B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 389B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 388B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 388B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 384B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 377B </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 340B </span>","children":null,"spread":false},{"title":"adder <span style='color:#111;'> 154.50KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 579.17KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 292.78KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 244.17KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 227.34KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 186.49KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 175.55KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 175.53KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 138.32KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 113.13KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 110.37KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 101.33KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 95.80KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 95.79KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 92.99KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 82.88KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 82.88KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 75.27KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 69.29KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 64.81KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 63.93KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 60.06KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 60.06KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 58.39KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 57.68KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 55.24KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 52.21KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 51.57KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 51.34KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 49.37KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 45.64KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 43.07KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 39.68KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 39.60KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 37.73KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 37.63KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 37.10KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 37.09KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 36.95KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 36.66KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 36.16KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 35.74KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 34.16KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 33.76KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 33.40KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 32.63KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 31.69KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 31.67KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 29.30KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 28.76KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 28.36KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 28.34KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 27.24KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 26.93KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 26.93KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 26.28KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 26.03KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 25.37KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 25.35KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 25.35KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 25.14KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 24.96KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 24.66KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 24.62KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 23.51KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 23.28KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 23.13KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 23.12KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 23.03KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 22.92KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 22.80KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]