FilterPro+Tina设计并实现的带通滤波器(内含PCB）

[{"title":"（ 45 个子文件 1.16MB ） FilterPro+Tina设计并实现的带通滤波器(内含PCB）","children":[{"title":"带通滤波器","children":[{"title":"History","children":[{"title":"2018-9-20.~(1).PrjPcb.Zip <span style='color:#111;'> 3.73KB </span>","children":null,"spread":false}],"spread":true},{"title":"2018-9-20.PcbDocPreview <span style='color:#111;'> 39.40KB </span>","children":null,"spread":false},{"title":"2018-9-20.PrjPcb <span style='color:#111;'> 31.59KB </span>","children":null,"spread":false},{"title":"Project Logs for 2018-9-20","children":[{"title":"2018-9-20 PCB ECO 2018-9-25 11-15-45.LOG <span style='color:#111;'> 10.17KB </span>","children":null,"spread":false},{"title":"PCB1 PCB ECO 2018-11-28 15-50-43.LOG <span style='color:#111;'> 230B </span>","children":null,"spread":false},{"title":"2018-9-20 PCB ECO 2018-9-25 11-17-11.LOG <span style='color:#111;'> 322B </span>","children":null,"spread":false},{"title":"2018-9-20 SCH ECO 2018-11-26 10-39-41.LOG <span style='color:#111;'> 1.31KB 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</span>","children":null,"spread":false},{"title":"2018-9-20 PCB ECO 2018-9-25 16-17-20.LOG <span style='color:#111;'> 234B </span>","children":null,"spread":false},{"title":"2018-9-20 SCH ECO 2018-11-28 15-41-23.LOG <span style='color:#111;'> 2.88KB </span>","children":null,"spread":false},{"title":"2018-9-20 PCB ECO 2018-9-25 16-38-20.LOG <span style='color:#111;'> 447B </span>","children":null,"spread":false}],"spread":false},{"title":"2018-9-20.PrjPcbStructure <span style='color:#111;'> 51B </span>","children":null,"spread":false},{"title":"PcbLib1.PcbLib <span style='color:#111;'> 38.00KB </span>","children":null,"spread":false},{"title":"2018-12-11.PcbDocPreview <span style='color:#111;'> 39.40KB </span>","children":null,"spread":false},{"title":"2018-12-11.PcbDoc <span style='color:#111;'> 1.33MB </span>","children":null,"spread":false},{"title":"PCB1.PcbDocPreview <span style='color:#111;'> 4.45KB </span>","children":null,"spread":false},{"title":"2018-9-20.SchDocPreview <span style='color:#111;'> 56.47KB </span>","children":null,"spread":false},{"title":"Project Outputs for 2018-9-20","children":[{"title":"Design Rule Check - 2018-9-20.drc <span style='color:#111;'> 13.22KB </span>","children":null,"spread":false},{"title":"Design Rule Check - 2018-9-20.html <span style='color:#111;'> 143.65KB </span>","children":null,"spread":false}],"spread":true},{"title":"Schlib1.SchLib <span style='color:#111;'> 11.50KB </span>","children":null,"spread":false},{"title":"2018-9-20.SchDoc <span style='color:#111;'> 212.00KB </span>","children":null,"spread":false},{"title":"PCB1.PcbDoc <span style='color:#111;'> 80.50KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]