CY7C68013a的slave fifo固件例程 源码
上传了CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，本人亲测，没有错误，可以编译成功，需要的朋友快快下载
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[{"title":"（ 64 个子文件 218KB ） CY7C68013a的slave fifo固件例程 源码","children":[{"title":"SLAVE FIFO 16BITS","children":[{"title":"FX2 Slave FIFO","children":[{"title":"tcxmaster.LST <span style='color:#111;'> 79.40KB </span>","children":null,"spread":false},{"title":"USBJmpTb.LST <span style='color:#111;'> 12.43KB </span>","children":null,"spread":false},{"title":"DSCR.LST <span style='color:#111;'> 16.18KB </span>","children":null,"spread":false},{"title":"FW.LST <span style='color:#111;'> 78.23KB </span>","children":null,"spread":false},{"title":"tcxmaster_Uv2.Bak <span style='color:#111;'> 2.32KB </span>","children":null,"spread":false},{"title":"tcxmaster.uvproj <span style='color:#111;'> 13.83KB </span>","children":null,"spread":false},{"title":"tcxmaster.uvopt <span style='color:#111;'> 8.80KB </span>","children":null,"spread":false},{"title":"tcxmaster.opt.bak <span style='color:#111;'> 1.51KB </span>","children":null,"spread":false},{"title":"dscr.a51 <span style='color:#111;'> 7.05KB </span>","children":null,"spread":false},{"title":"build.bat <span style='color:#111;'> 1.89KB </span>","children":null,"spread":false},{"title":"tcxmaster.bix <span style='color:#111;'> 8.00KB </span>","children":null,"spread":false},{"title":"tcxmaster.iic <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"USBJmpTb.a51 <span style='color:#111;'> 4.58KB </span>","children":null,"spread":false},{"title":"tcxmaster.c <span style='color:#111;'> 11.08KB </span>","children":null,"spread":false},{"title":"Hex2bix.exe <span style='color:#111;'> 184.05KB </span>","children":null,"spread":false},{"title":"FW.OBJ <span style='color:#111;'> 7.03KB </span>","children":null,"spread":false},{"title":"FX2 xFIFO 8-bit Async Build ENV.pif <span style='color:#111;'> 967B </span>","children":null,"spread":false},{"title":"Hex2Bix.bat <span style='color:#111;'> 46B </span>","children":null,"spread":false},{"title":"tcxmaster.lnp <span style='color:#111;'> 157B </span>","children":null,"spread":false},{"title":"tcxmaster.uvgui.eaggle <span style='color:#111;'> 72.83KB </span>","children":null,"spread":false},{"title":"tcxmaster.plg <span style='color:#111;'> 2.22KB </span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'> 464B </span>","children":null,"spread":false},{"title":"tcxmaster.M51 <span style='color:#111;'> 110.59KB </span>","children":null,"spread":false},{"title":"tcxmaster.Uv2.bak <span style='color:#111;'> 2.32KB </span>","children":null,"spread":false},{"title":"tcxmaster <span style='color:#111;'> 27.74KB </span>","children":null,"spread":false},{"title":"USBJmpTb.OBJ <span style='color:#111;'> 1.93KB </span>","children":null,"spread":false},{"title":"tcxmaster.OBJ <span style='color:#111;'> 12.02KB </span>","children":null,"spread":false},{"title":"Ezusb.lib <span style='color:#111;'> 35.57KB </span>","children":null,"spread":false},{"title":"tcxmaster_Opt.Bak <span style='color:#111;'> 1.51KB </span>","children":null,"spread":false},{"title":"readme.txt <span style='color:#111;'> 6.56KB </span>","children":null,"spread":false},{"title":"USBJmpTb._ia <span style='color:#111;'> 58B </span>","children":null,"spread":false},{"title":"tcxmaster.hex <span style='color:#111;'> 7.41KB </span>","children":null,"spread":false},{"title":"DSCR.OBJ <span style='color:#111;'> 1015B </span>","children":null,"spread":false},{"title":"fw.c <span style='color:#111;'> 13.18KB </span>","children":null,"spread":false}],"spread":false},{"title":"FPGA","children":[{"title":"USB_FPGA.qsf <span style='color:#111;'> 5.64KB </span>","children":null,"spread":false},{"title":"USB_FPGA.sim.rpt <span style='color:#111;'> 90.50KB </span>","children":null,"spread":false},{"title":"USB_FPGA.tan.rpt <span style='color:#111;'> 193.90KB </span>","children":null,"spread":false},{"title":"USB_FPGA.map.summary <span style='color:#111;'> 332B </span>","children":null,"spread":false},{"title":"USB_FPGA.qpf <span style='color:#111;'> 902B </span>","children":null,"spread":false},{"title":"USB_FPGA.cdf <span style='color:#111;'> 303B </span>","children":null,"spread":false},{"title":"db","children":[{"title":"USB_FPGA.sld_design_entry.sci <span style='color:#111;'> 154B </span>","children":null,"spread":false},{"title":"USB_FPGA.eco.cdb <span style='color:#111;'> 161B </span>","children":null,"spread":false},{"title":"altsyncram_lk81.tdf <span style='color:#111;'> 20.50KB </span>","children":null,"spread":false},{"title":"USB_FPGA.db_info <span style='color:#111;'> 137B </span>","children":null,"spread":false}],"spread":true},{"title":"USB_FPGA.sof <span style='color:#111;'> 137.23KB </span>","children":null,"spread":false},{"title":"USB_FPGA.vhd.bak <span style='color:#111;'> 4.23KB </span>","children":null,"spread":false},{"title":"USB_FPGA.fit.smsg <span style='color:#111;'> 411B </span>","children":null,"spread":false},{"title":"USB_FPGA.vwf <span style='color:#111;'> 40.01KB </span>","children":null,"spread":false},{"title":"USB_FPGA.qws <span style='color:#111;'> 534B </span>","children":null,"spread":false},{"title":"prev_cmp_USB_FPGA.qmsg <span style='color:#111;'> 18.53KB </span>","children":null,"spread":false},{"title":"USB_FPGA.map.rpt <span style='color:#111;'> 38.46KB </span>","children":null,"spread":false},{"title":"USB_FPGA.fit.eqn <span style='color:#111;'> 70.57KB </span>","children":null,"spread":false},{"title":"USB_FPGA.vhd <span style='color:#111;'> 4.76KB </span>","children":null,"spread":false},{"title":"USB_FPGA.tan.summary <span style='color:#111;'> 1.72KB </span>","children":null,"spread":false},{"title":"USB_FPGA.asm.rpt <span style='color:#111;'> 8.52KB </span>","children":null,"spread":false},{"title":"USB_FPGA.pof <span style='color:#111;'> 512.20KB </span>","children":null,"spread":false},{"title":"USB_FPGA.fit.summary <span style='color:#111;'> 424B </span>","children":null,"spread":false},{"title":"USB_FPGA.pin <span style='color:#111;'> 29.55KB </span>","children":null,"spread":false},{"title":"USB_FPGA_assignment_defaults.qdf <span style='color:#111;'> 27.33KB </span>","children":null,"spread":false},{"title":"USB_FPGA.fit.rpt <span style='color:#111;'> 144.98KB </span>","children":null,"spread":false},{"title":"USB_FPGA.map.eqn <span style='color:#111;'> 62.89KB </span>","children":null,"spread":false},{"title":"_desktop.ini <span style='color:#111;'> 9B </span>","children":null,"spread":false},{"title":"USB_FPGA.flow.rpt <span style='color:#111;'> 3.68KB </span>","children":null,"spread":false},{"title":"USB_FPGA.done <span style='color:#111;'> 26B </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]
评论信息
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m0_37701128 :资料有一定参考，可以借鉴2020-07-28 -
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xiaohairong1988 :修改后可以用2019-07-27
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yongli2008 :很简单，已成功实现了！谢谢！2018-06-24
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xjtu_linxi :参考价值很高，感谢楼主分享~2016-01-08
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qq_32400205 :非常实用，正是所需要的，感谢。2015-10-30
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