[{"title":"( 5 个子文件 16.18MB ) 最全Verilog、SystemVerilog IEEE标准","children":[{"title":"1995 V:IEEE1364-1995_Verilog_lrm.pdf <span style='color:#111;'> 6.22MB </span>","children":null,"spread":false},{"title":"2001 V:IEEE1364-2001 Verilog lrm.pdf <span style='color:#111;'> 4.41MB </span>","children":null,"spread":false},{"title":"2005SV:IEEE Std 1800-2005(System Verilog).pdf <span style='color:#111;'> 6.31MB </span>","children":null,"spread":false},{"title":"2005 V:Verilog IEEE Std(1364-2005).pdf <span style='color:#111;'> 3.22MB </span>","children":null,"spread":false},{"title":"2009SV:IEEE Standard for SystemVerilog—Unified Hardware Design,Specification, and VerificationLanguage.pdf <span style='color:#111;'> 11.04MB </span>","children":null,"spread":false}],"spread":true}]