VHDL实现一位全加器，并串行实现四位全加器

[{"title":"（ 112 个子文件 213KB ） VHDL实现一位全加器，并串行实现四位全加器","children":[{"title":"fourbitadder.map.summary <span style='color:#111;'> 324B </span>","children":null,"spread":false},{"title":"onebitadder.pof <span style='color:#111;'> 128.18KB </span>","children":null,"spread":false},{"title":"fourbitadder.cdf <span style='color:#111;'> 289B </span>","children":null,"spread":false},{"title":"fourbitadder.tan.rpt <span style='color:#111;'> 8.14KB </span>","children":null,"spread":false},{"title":"onebitadder.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]