cordic的verilog实现包含testbench

上传者: xingzhe22222 | 上传时间: 2022-10-28 14:09:34 | 文件大小: 74KB | 文件类型: ZIP
用veriolg实现16级流水线结构的cordic加速器,该加速器可求出正弦,余弦值。文件中采用了两种测试机制。一种是从外部读取测试向量;另一种是用循环扫描的方式测试。测试结果都已文件的形式输出,并且在控制台上打印。

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