[{"title":"( 9 个子文件 5KB ) 异步FIFO Verilog HDL,包含所有标志位,通过验证","children":[{"title":"ayn_fifo_success","children":[{"title":"rptr_almost_empty.v <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"sync_w2r.v <span style='color:#111;'> 497B </span>","children":null,"spread":false},{"title":"fifo1.v <span style='color:#111;'> 3.70KB </span>","children":null,"spread":false},{"title":"wptr_almost_full.v <span style='color:#111;'> 2.24KB </span>","children":null,"spread":false},{"title":"fifomen.v <span style='color:#111;'> 716B </span>","children":null,"spread":false},{"title":"rptr_empty.v <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"wptr_full.v <span style='color:#111;'> 1.45KB </span>","children":null,"spread":false},{"title":"wptr_half_full.v <span style='color:#111;'> 1.08KB </span>","children":null,"spread":false},{"title":"sync_r2w.v <span style='color:#111;'> 458B </span>","children":null,"spread":false}],"spread":true}],"spread":true}]