[{"title":"( 11 个子文件 814KB ) 夏闻宇Verilog教程","children":[{"title":"夏闻宇Verilog教程","children":[{"title":"第四章 不同抽象级别的Verilog HDL模型.doc <span style='color:#111;'> 431.59KB </span>","children":null,"spread":false},{"title":"第七章 有限状态机和可综合风格的Verilog HDL.doc <span style='color:#111;'> 1.06MB </span>","children":null,"spread":false},{"title":"第九章虚拟器件和虚拟接口模型以及它们在大型数字系统设计中的作用.doc <span style='color:#111;'> 276.25KB </span>","children":null,"spread":false},{"title":"第五章 基本运算逻辑和它们的Verilog HDL模型.doc <span style='color:#111;'> 246.00KB </span>","children":null,"spread":false},{"title":"第六章 运算和数据流动控制逻辑.doc <span style='color:#111;'> 164.00KB </span>","children":null,"spread":false},{"title":"第一章 数字信号处理计算程序算法和硬线逻辑的基本概念.doc <span style='color:#111;'> 46.00KB </span>","children":null,"spread":false},{"title":"第八章 可综合的VerilogHDL设计实例简化的RISC CPU设计简介.doc <span style='color:#111;'> 703.50KB </span>","children":null,"spread":false},{"title":"学习笔记.txt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"第三章 Verilog HDL的基本语法.doc <span style='color:#111;'> 918.33KB </span>","children":null,"spread":false},{"title":"~$第四章.doc <span style='color:#111;'> 162B </span>","children":null,"spread":false},{"title":"第二章 Verilog HDL设计方法概述.doc <span style='color:#111;'> 236.00KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]