[{"title":"( 5195 个子文件 11.42MB ) Verilog HDL数字控制系统设计实例","children":[{"title":"Position_adc_ctrl.sim.rpt <span style='color:#111;'> 4.33KB </span>","children":null,"spread":false},{"title":"Position_adc_ctrl.fit.summary <span style='color:#111;'> 429B </span>","children":null,"spread":false},{"title":"Position_adc_ctrl.map.rpt <span style='color:#111;'> 13.19KB </span>","children":null,"spread":false},{"title":"Position_adc_ctrl.vwf <span style='color:#111;'> 15.53KB </span>","children":null,"spread":false},{"title":"Position_adc_ctrl.fit.eqn <span style='color:#111;'> 5.85KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]