[{"title":"( 126 个子文件 1.01MB ) 基于FPGA用VHDL语言设计的12小时制时钟","children":[{"title":"引脚配置图.jpg <span style='color:#111;'> 42.39KB </span>","children":null,"spread":false},{"title":"hour12.qsf <span style='color:#111;'> 2.49KB </span>","children":null,"spread":false},{"title":"hour12.pof <span style='color:#111;'> 128.20KB </span>","children":null,"spread":false},{"title":"hour12.qws <span style='color:#111;'> 542B </span>","children":null,"spread":false},{"title":"hour12.tan.summary <span style='color:#111;'> 1.47KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]