基于FPGA的数字电子时钟

上传者: 52404225 | 上传时间: 2023-02-14 19:42:52 | 文件大小: 8.91MB | 文件类型: RAR
基于FPGA的数字电子时钟,采用verilog语言编写,引脚已经设置好,直接运行上传即可使用。本文是用verilog语言来描述一个基于FPGA的多功能数字电子时钟的设计,该设计具备时间显示,准确计时,时间校准, 定时闹钟等功能。本文首先介绍了需要完成的工作,然后介绍了系统整体设计以及源代码开发过程。源代码首先在Quartus软件上进行仿真、综合,通过后下载到正点原子新启点开发板上,在FPGA器件上的试验结果表明上述功能全部正确,工作稳定良好。 1、能够用数码管或液晶屏显示时、分和秒(采用24小时进制); 2、具有按键校时功能,对小时和分单独校时,对分校时时,停止向小时进位; 3、具有闹钟功能,闹钟铃声为自主设计的用蜂鸣器发出的声音; 4、通过按键设置闹钟功能,且自动停闹和手动操作停闹; 5、其它创意设计:增加闹钟模式开启指示灯和闹铃提示灯;可以作为秒表使用。

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