基于 FPGA 的 I2C 总线模拟,采用 Verilog HDL 语言编写

上传者: 43870101 | 上传时间: 2023-01-03 17:44:58 | 文件大小: 241KB | 文件类型: ZIP
基于FPGA的I2C总线模拟,采用Verilog HDL语言编写 (FPGA-based I2C bus simulation, using Verilog HDL.)

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