基于Zynq7020的Uart和PWM的Verilog HDL代码

[{"title":"（ 8 个子文件 91KB ） 基于Zynq7020的Uart和PWM的Verilog HDL代码","children":[{"title":"VerilogCode","children":[{"title":"imagneto.v <span style='color:#111;'> 8.92KB </span>","children":null,"spread":false},{"title":"uart.v <span style='color:#111;'> 7.95KB </span>","children":null,"spread":false},{"title":"verilog模块端口定义规则.jpg <span style='color:#111;'> 96.54KB </span>","children":null,"spread":false},{"title":"fifo.v <span style='color:#111;'> 2.53KB </span>","children":null,"spread":false},{"title":"testbench.v <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"clk.v <span style='color:#111;'> 2.31KB </span>","children":null,"spread":false},{"title":"testbench_imagneto.v <span style='color:#111;'> 1.66KB </span>","children":null,"spread":false},{"title":"pwm.v <span style='color:#111;'> 2.24KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]