[{"title":"( 179 个子文件 56KB ) HDLBits-Solutions-Verilog-master.rar","children":[{"title":"6_AND gate.v <span style='color:#111;'> 94B </span>","children":null,"spread":false},{"title":"5_Inverter.v <span style='color:#111;'> 80B </span>","children":null,"spread":false},{"title":"8_XNOR gate.v <span style='color:#111;'> 97B </span>","children":null,"spread":false},{"title":"7_NOR gate.v <span style='color:#111;'> 97B </span>","children":null,"spread":false},{"title":"9_Declaring wires.v <span style='color:#111;'> 224B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]