[{"title":"( 173 个子文件 4.85MB ) FPGA Verilog串口屏控制源码及测试工程,使用Altera FPGA测试。","children":[{"title":"HMI_Control.sta.rpt <span style='color:#111;'> 157.46KB </span>","children":null,"spread":false},{"title":"HMI_Control.sta.summary <span style='color:#111;'> 973B </span>","children":null,"spread":false},{"title":"HMI_Control.merge.summary <span style='color:#111;'> 478B </span>","children":null,"spread":false},{"title":"HMI_Control.map.smsg <span style='color:#111;'> 414B </span>","children":null,"spread":false},{"title":"HMI_Control.jdi <span style='color:#111;'> 229B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]