verilog-uart:Verilog UART
Verilog UART 自述文件
有关更多信息和更新： :
GitHub 存储库： :
介绍
这是一个基本的 UART 到 AXI Stream IP 核，用 Verilog 编写，带有 cocotb 测试平台。
文档
核心的主要代码存在于 rtl 子目录中。 uart_rx.v 和 uart_tx.v 文件是实际的实现，uart.v 只是实例化两个模块并建立了几个内部连接。
UART 发送器和接收器都使用单个发送或接收引脚。 这些模块采用一个参数 DATA_WIDTH，该参数指定数据总线的宽度和实际通信数据字的长度。 8 位接口的默认值为 8。 预分频输入决定了数据速率 - 它应该设置为 Fclk /（波特 * 8）。 这是一个输入而不是参数，因此可以在运行时更改它，尽管它不在内部缓冲，因此应小心避免损坏数据。 用户设计的主要接口是一个 AXI4-Stream 接口，它由
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