verilog-i2c:用于 FPGA 实现的 Verilog I2C 接口

上传者: 42144086 | 上传时间: 2023-01-03 17:36:44 | 文件大小: 88KB | 文件类型: ZIP
Verilog I2C 接口 有关更多信息和更新: : GitHub 存储库: : 介绍 I2C 接口组件。 包括带有智能总线协同仿真端点的完整 MyHDL 测试平台。 文档 i2c_init 模块 通过 I2C 进行外设初始化的模板模块。 当一个或多个外围设备(即 PLL 芯片、抖动衰减器、时钟复用器等)需要在上电时初始化而不使用通用处理器时使用。 i2c_master 模块 I2C 主模块带有 AXI 流接口来控制逻辑。 i2c_master_axil 模块 具有 32 位 AXI lite 从接口的 I2C 主模块。 i2c_master_wbs_8 模块 具有8位Wishbone从接口的I2C主模块。 i2c_master_wbs_16 模块 带有 16 位 Wishbone 从接口的 I2C 主模块。 i2c_slave 模块 带有 AXI 流接口以控制逻辑的 I2C

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