compression-chisel-源码

上传者: 42139460 | 上传时间: 2021-03-14 19:09:47 | 文件大小: 55KB | 文件类型: ZIP
长度压缩和缩减 长度压缩 长度-用可变数量的位压缩可变数量的像素,并输出标头和混洗的数据。 主文件: 运行测试: make lengthtest测试 生成Verilog:生成make lengthverilog 单还原阶段(合并) 接收两个大小相等的Vecs数据及其长度(作为字数而非位),并输出合并的数据及其长度 主文件: 运行测试: make mergetest 生成Verilog: make mergeverilog 完全还原v1 接收来自64个压缩器的标头和数据,并吐出一个包含合并数据的单个UInt 10496位宽 主文件: 运行测试:由于内存问题,无法进行 生成Verilog: make reductionverilog Verilog 全面还原v2(更好) 从至少4个压缩器中接收标头和数据,并输出一个16位UInt的Vec,所有标头在前面分组在一起,合并后的

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