verilog-ethernet:用于FPGA实现的Verilog以太网组件
Verilog以太网组件自述文件
有关更多信息和更新： :
GitHub存储库： :
介绍
以太网相关组件的集合，用于千兆位，10G和25G数据包处理（8位和64位数据路径）。 包括用于处理以太网帧以及IP，UDP和ARP的模块，以及用于构建完整UDP / IP堆栈的组件。 包括用于千兆位和10G / 25G的MAC模块，一个10G / 25G PCS / PMA PHY模块以及一个10G / 25G组合MAC / PCS / PMA模块。 包括各种与PTP相关的组件，用于实施需要精确时间同步的系统。 还包括利用完整cocotb测试平台。
仅对于IP和ARP支持，请使用ip_complete（1G）或ip_complete_64（10G / 25G）。
要获得UDP，IP和ARP支持，请使用udp_complete（1G）或udp_complete_64（10G / 25G
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