wbuart32:一个简单的,经过正式验证的基本UART控制器-源码

上传者: 42135773 | 上传时间: 2021-09-16 16:37:38 | 文件大小: 371KB | 文件类型: ZIP
另一个Wishbone(甚至AXI-lite)控制的UART 由于已经有许多人牵手提出了UART内核,...对我来说,这似乎也很好完美的(很好)对全部事情从一开始就写...我自己的UART内核。 [] 此Verilog内核包含两个UART模块,,。 每一个都可以通过一个32位字配置为几乎任何波特率,一个或两个停止位,五个到八个数据位以及奇,偶,标记或空间奇偶校验。 如果您正在寻找包含所有这些功能的示例Verilog UART模块,那么您就找到了它。 该模块不仅包括简单的发送和接收,还包括相当通用的 。 对于那些正在寻找相当简单的FIFO的用户,无论是您的UART功能还是其他功能,您也都可以找到它。 如果您正在寻找启用了叉骨的外围设备,则此模块提供两种配置方法:可以包含在另一个更大的叉骨模块中,可以自己完成—与集成的FIFO和一个FIFO状态寄存器。 如果您想要的是AXI-lite

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