SystemVerilogSHA256 ：（系统-）Verilog开源FPGA Miner中的SHA256-源码

[{"title":"（ 17 个子文件 88KB ） SystemVerilogSHA256 ：（系统-）Verilog开源FPGA Miner中的SHA256-源码","children":[{"title":"SystemVerilogSHA256-master","children":[{"title":"miner.sv <span style='color:#111;'> 1.45KB </span>","children":null,"spread":false},{"title":"sha_256_tb.vcd <span style='color:#111;'> 75.70KB </span>","children":null,"spread":false},{"title":"sha_padder_tb.vcd <span style='color:#111;'> 1.41KB </span>","children":null,"spread":false},{"title":"sha_mainloop_tb.vcd <span style='color:#111;'> 74.21KB </span>","children":null,"spread":false},{"title":"sha_padder.dot <span style='color:#111;'> 997B </span>","children":null,"spread":false},{"title":"miner_tb.sv <span style='color:#111;'> 710B </span>","children":null,"spread":false},{"title":"sha_mainloop.dot <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"sha_mainloop_tb.sv <span style='color:#111;'> 1.00KB </span>","children":null,"spread":false},{"title":"LICENSE.md <span style='color:#111;'> 34.32KB </span>","children":null,"spread":false},{"title":"sha_mainloop.sv <span style='color:#111;'> 3.95KB </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 3.00KB </span>","children":null,"spread":false},{"title":"sha_256_tb.sv <span style='color:#111;'> 837B </span>","children":null,"spread":false},{"title":"sha_padder.sv <span style='color:#111;'> 921B </span>","children":null,"spread":false},{"title":"sha_padder.pdf <span style='color:#111;'> 12.95KB </span>","children":null,"spread":false},{"title":"sha_padder_tb.sv <span style='color:#111;'> 364B </span>","children":null,"spread":false},{"title":"miner_tb.vcd <span style='color:#111;'> 228.29KB </span>","children":null,"spread":false},{"title":"sha_256.sv <span style='color:#111;'> 526B </span>","children":null,"spread":false}],"spread":false}],"spread":true}]