verilog-axi:用于FPGA实现的Verilog AXI组件
Verilog AXI组件自述文件
有关更多信息和更新： :
GitHub存储库： :
介绍
AXI4和AXI4精简总线组件的集合。 大多数组件的接口宽度均可完全参数化。 包括利用完整cocotb测试平台。
文献资料
axi_adapter模块
具有可设置参数的数据和地址接口宽度的AXI宽度适配器模块。 支持INCR突发类型和窄突发。 包装axi_adapter_rd和axi_adapter_wr。
axi_adapter_rd模块
具有可设置参数的数据和地址接口宽度的AXI宽度适配器模块。 支持INCR突发类型和窄突发。
axi_adapter_wr模块
具有可设置参数的数据和地址接口宽度的AXI宽度适配器模块。 支持INCR突发类型和窄突发。
axi_axil_adapter模块
具有可设置参数的数据和地址接口宽度的AXI至AXI lite转换器和宽度适配器模块。 支持IN
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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明