riscv-cpu-verilog-code：大二上学期MS108大作业，verilog实现五级流水cpu-源码

[{"title":"（ 26 个子文件 183KB ） riscv-cpu-verilog-code：大二上学期MS108大作业，verilog实现五级流水cpu-源码","children":[{"title":"riscv-cpu-verilog-code-master","children":[{"title":"src","children":[{"title":"ifid.v <span style='color:#111;'> 741B </span>","children":null,"spread":false},{"title":"riscv_top.v <span style='color:#111;'> 3.41KB </span>","children":null,"spread":false},{"title":"memwb.v <span style='color:#111;'> 731B </span>","children":null,"spread":false},{"title":"hci.v <span style='color:#111;'> 19.68KB </span>","children":null,"spread":false},{"title":"pc_reg.v <span style='color:#111;'> 606B </span>","children":null,"spread":false},{"title":"stall.v <span style='color:#111;'> 516B </span>","children":null,"spread":false},{"title":"id.v <span style='color:#111;'> 7.07KB </span>","children":null,"spread":false},{"title":"if - backup.v <span style='color:#111;'> 2.20KB </span>","children":null,"spread":false},{"title":"idex.v <span style='color:#111;'> 1.58KB </span>","children":null,"spread":false},{"title":"ex.v <span style='color:#111;'> 7.46KB </span>","children":null,"spread":false},{"title":"exmem.v <span style='color:#111;'> 1.67KB </span>","children":null,"spread":false},{"title":"tmp.v <span style='color:#111;'> 2.53KB </span>","children":null,"spread":false},{"title":"ram.v <span style='color:#111;'> 821B </span>","children":null,"spread":false},{"title":"mem.v <span style='color:#111;'> 5.27KB </span>","children":null,"spread":false},{"title":"memctrl.v <span style='color:#111;'> 3.79KB </span>","children":null,"spread":false},{"title":"cpu.v <span style='color:#111;'> 8.66KB </span>","children":null,"spread":false},{"title":"common","children":[{"title":"uart","children":[{"title":"uart_baud_clk.v <span style='color:#111;'> 2.36KB </span>","children":null,"spread":false},{"title":"uart_tx.v <span style='color:#111;'> 6.32KB </span>","children":null,"spread":false},{"title":"uart.v <span style='color:#111;'> 4.77KB </span>","children":null,"spread":false},{"title":"uart_rx.v <span style='color:#111;'> 6.18KB </span>","children":null,"spread":false}],"spread":false},{"title":"block_ram","children":[{"title":"block_ram.v <span style='color:#111;'> 3.17KB </span>","children":null,"spread":false}],"spread":false},{"title":"fifo","children":[{"title":"fifo.v <span style='color:#111;'> 4.06KB </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"register.v <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"if.v <span style='color:#111;'> 1.69KB </span>","children":null,"spread":false}],"spread":false},{"title":"sim","children":[{"title":"testbench.v <span style='color:#111;'> 323B </span>","children":null,"spread":false}],"spread":true},{"title":"sim_status.docx <span style='color:#111;'> 171.46KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]