[{"title":"( 5 个子文件 1KB ) 利用Verilog实现数字秒表(基本逻辑设计分频器练习)","children":[{"title":"StopWatch.v <span style='color:#111;'> 343B </span>","children":null,"spread":false},{"title":"StopWatchTest.v <span style='color:#111;'> 380B </span>","children":null,"spread":false},{"title":"SecondClk.v <span style='color:#111;'> 355B </span>","children":null,"spread":false},{"title":"Counter.v <span style='color:#111;'> 844B </span>","children":null,"spread":false},{"title":"FrequencyDivision10.v <span style='color:#111;'> 243B </span>","children":null,"spread":false}],"spread":true}]