Performance Estimation Techniques With MPSoC Transaction-Accurate Models

Efficient design of Multi-Processor System-On-Chip (MPSoC) requires early, fast and accurate performance estimation techniques. In this paper, we present new techniques based on fine-grained code analysis to estimate accurate performance during simulation of MPSoC Transaction Accurate Models. First, a GCC profiling tool is applied in the native simulation process. Based on the profiling result, an instruction analyzer of the target CPU architecture is proposed to analyze the cycle cost of C code