Matlab代码verilog-bchverilog:用于在Verilog中为任意k和t生成展开的，缩短的，系统化的BCH编解码器的MATLA

[{"title":"（ 4 个子文件 5KB ） Matlab代码verilog-bchverilog:用于在Verilog中为任意k和t生成展开的，缩短的，系统化的BCH编解码器的MATLA","children":[{"title":"bchverilog-master","children":[{"title":"bchverilog.m <span style='color:#111;'> 14.26KB </span>","children":null,"spread":false},{"title":"LICENSE <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"hammingverilog.m <span style='color:#111;'> 6.45KB </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 269B </span>","children":null,"spread":false}],"spread":true}],"spread":true}]