matlab精度检验代码-zynq_tdc:RedPitayaZynq-7010SoC中的高分辨率时间数字转换器

上传者: 38557980 | 上传时间: 2023-02-26 14:56:10 | 文件大小: 901KB | 文件类型: ZIP
matlab精度检验代码ZYNQ时间数字转换器 Red Pitaya Zynq-7010 SoC中的快速高分辨率时间数字转换器 作者:米歇尔·亚当尼克(Michel Adamic) 表现核心频率:350 MHz 延迟线抽头数:192(可配置) 每个通道的时间分辨率:> 11 ps 精度:<10 ppm DNL:-1至+4.5 LSB INL:+0.5至+8.5 LSB 测量范围:47.9毫秒死区时间:〜14 ns 最高速度:〜70 MS / s 档案 贸易发展局主项目,包含AXI TDC内核的设计。 使用VHDL源文件和3个Vivado配置的Xilinx IP(BRAM,BRAM控制器,AXI GPIO)。 需要包含“ MyPkg.vhd”。 AXI_TDC_IP Vivado创建的临时项目,用于将TDC打包到IP内核中。 TDC系统包含Zynq PS和多个TDC内核的顶层模块设计。 时钟:AXI互连期望100 MHz。 对于TDC内核,MMCME将其提高到350 MHz。 外部端口:每个TDC通道的命中信号。 模块“ testUnit”是用于测试的方波发生器,可以将其删除。 TDC通

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