[{"title":"( 20 个子文件 401KB ) 多周期CPU(verilog实现/含实验文档)","children":[{"title":"Lab6 多周期CPU.docx <span style='color:#111;'> 441.58KB </span>","children":null,"spread":false},{"title":"lab6 多周期CPU","children":[{"title":"mem.coe <span style='color:#111;'> 527B </span>","children":null,"spread":false},{"title":"Mux_MemtoReg.v <span style='color:#111;'> 746B </span>","children":null,"spread":false},{"title":"Register_Data.v <span style='color:#111;'> 710B </span>","children":null,"spread":false},{"title":"Register_File.v <span style='color:#111;'> 919B </span>","children":null,"spread":false},{"title":"Mux4_1.v <span style='color:#111;'> 693B </span>","children":null,"spread":false},{"title":"Mux_RegDst.v <span style='color:#111;'> 735B </span>","children":null,"spread":false},{"title":"PC.v <span style='color:#111;'> 698B </span>","children":null,"spread":false},{"title":"Sign_Extend.v <span style='color:#111;'> 688B </span>","children":null,"spread":false},{"title":"Register_Instr.v <span style='color:#111;'> 730B </span>","children":null,"spread":false},{"title":"ALU.v <span style='color:#111;'> 961B </span>","children":null,"spread":false},{"title":"Mux_PCSrc.v <span style='color:#111;'> 781B </span>","children":null,"spread":false},{"title":"Register_ALUOut.v <span style='color:#111;'> 747B </span>","children":null,"spread":false},{"title":"Mux_ALUSrcA.v <span style='color:#111;'> 749B </span>","children":null,"spread":false},{"title":"CPU.v <span style='color:#111;'> 2.85KB </span>","children":null,"spread":false},{"title":"Mux_ALUSrcB.v <span style='color:#111;'> 975B </span>","children":null,"spread":false},{"title":"Register_A.v <span style='color:#111;'> 837B </span>","children":null,"spread":false},{"title":"Memory.v <span style='color:#111;'> 729B </span>","children":null,"spread":false},{"title":"control.v <span style='color:#111;'> 3.53KB </span>","children":null,"spread":false},{"title":"Mux_lorD.v <span style='color:#111;'> 823B </span>","children":null,"spread":false}],"spread":false}],"spread":true}]