基于UVM的AHB总线SRAM控制器设计验证平台设计

上传者: wczzmmp2 | 上传时间: 2022-08-11 21:03:36 | 文件大小: 1.28MB | 文件类型: ZIP
1、设计基于AHB总线的SRAM读写控制器:根据AHB总线输入hsize与haddr自动选择块与片选,在原有基础上,增加了8位数据与16位数据深度,即当hsize选择8位数据传输时,数据深度为8*8k=2^16,当选择16位时,数据深度为4*8k=2^15,当数据为32位时,深度与原有一样为2*8k=2^14。 2、设计基于UVM的验证框架:设计两级sequencer与sequence分别控制读写、设计两个case分别为边写边读与写满读空。

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