一本FPGA方面未出版的书

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style='color:#111;'> 73.50KB </span>","children":null,"spread":false},{"title":"第5节 XPS软件的高级操作.doc <span style='color:#111;'> 107.00KB </span>","children":null,"spread":false},{"title":"第3节 基于ISE的开发流程.doc <span style='color:#111;'> 130.00KB </span>","children":null,"spread":false},{"title":"第3节 基于System Generator的DSP系统设计.doc <span style='color:#111;'> 86.50KB </span>","children":null,"spread":false},{"title":"第4节 Verilog HDL语言的描述语句.doc <span style='color:#111;'> 48.50KB </span>","children":null,"spread":false},{"title":"第6节 多通道FIR滤波器.doc <span style='color:#111;'> 59.00KB </span>","children":null,"spread":false},{"title":"第3节 FPGA的常用配置电路.doc <span style='color:#111;'> 105.00KB </span>","children":null,"spread":false},{"title":"第3节 EDK软件基本介绍.doc <span style='color:#111;'> 46.50KB </span>","children":null,"spread":false},{"title":"第2节 JTAG电路的原理与设计.doc <span style='color:#111;'> 38.50KB </span>","children":null,"spread":false},{"title":"第2节 FPGA芯片结构.doc <span style='color:#111;'> 51.50KB </span>","children":null,"spread":false},{"title":"第1节 可编程逻辑器件基础.doc <span style='color:#111;'> 28.50KB </span>","children":null,"spread":false},{"title":"第1节 高速数据连接功能简介--FPGA开发实用教程.doc <span style='color:#111;'> 28.50KB </span>","children":null,"spread":false},{"title":"第2节 实现吉比特高速串行I.doc <span style='color:#111;'> 44.50KB </span>","children":null,"spread":false},{"title":"第6节 EDK开发实例.doc <span style='color:#111;'> 51.00KB </span>","children":null,"spread":false},{"title":"第4节 Xilinx公司器件简介.doc.lnk <span style='color:#111;'> 426B </span>","children":null,"spread":false},{"title":"第3节 XtremeDSP模块功能介绍.doc <span style='color:#111;'> 25.50KB </span>","children":null,"spread":false},{"title":"第4节 XPS软件的基本操作.doc <span style='color:#111;'> 118.00KB </span>","children":null,"spread":false},{"title":"第6节 Xilinx FPGA芯片底层单元的使用.doc <span style='color:#111;'> 60.00KB </span>","children":null,"spread":false},{"title":"第3节 VerilogHDL语言的数据类型和运算符.doc <span style='color:#111;'> 50.50KB </span>","children":null,"spread":false},{"title":"第2节 HDL代码输入.doc <span style='color:#111;'> 60.50KB </span>","children":null,"spread":false},{"title":"第5节 半_并行FIR滤波器.doc <span style='color:#111;'> 35.00KB </span>","children":null,"spread":false},{"title":"第1节 ISE套件的介绍与安装.doc <span style='color:#111;'> 52.00KB </span>","children":null,"spread":false},{"title":"第2节 System Generator入门基础.doc <span style='color:#111;'> 34.50KB </span>","children":null,"spread":false},{"title":"第1节 FPGA配置电路综述.doc <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"第1节 可配置嵌入式系统.doc <span style='color:#111;'> 24.00KB </span>","children":null,"spread":false},{"title":"第1节 面向硬件电路的设计思维.doc <span style='color:#111;'> 57.50KB </span>","children":null,"spread":false},{"title":"第4节 约束文件的编写.doc <span style='color:#111;'> 53.00KB </span>","children":null,"spread":false},{"title":"第3节 Verilog建模与调试技巧.doc <span style='color:#111;'> 56.50KB </span>","children":null,"spread":false},{"title":"第5节 使用Xilinx PROM器件存储用户数据.doc <span style='color:#111;'> 30.50KB </span>","children":null,"spread":false},{"title":"第2节 优秀的HDL代码风格.doc <span style='color:#111;'> 85.00KB </span>","children":null,"spread":false},{"title":"第3节 基于Rocket I.doc <span style='color:#111;'> 109.00KB </span>","children":null,"spread":false},{"title":"第1节 System Generator的简介与安装--FPGA开发实用教程.doc <span style='color:#111;'> 36.50KB </span>","children":null,"spread":false},{"title":"第1节 数字信号概述.doc <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"第4节 Xilinx公司原语的使用方法1.doc <span style='color:#111;'> 70.50KB </span>","children":null,"spread":false},{"title":"第6节 开发实例.doc <span style='color:#111;'> 31.00KB </span>","children":null,"spread":false},{"title":"第2节 Xilinx嵌入式开发系统组成介绍.doc <span style='color:#111;'> 78.50KB </span>","children":null,"spread":false},{"title":"第4节 基于System Generator的硬件协仿真.doc <span style='color:#111;'> 42.00KB </span>","children":null,"spread":false},{"title":"第4节 乘累加结构的FIR滤波器.doc <span style='color:#111;'> 49.50KB </span>","children":null,"spread":false},{"title":"第2节 Verilog HDL基本程序结构.doc <span style='color:#111;'> 27.00KB </span>","children":null,"spread":false},{"title":"第3节 基于FPGA的开发流程.doc <span style='color:#111;'> 46.00KB </span>","children":null,"spread":false},{"title":"第5节 ystem Generator的高级应用.doc <span style='color:#111;'> 80.50KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]