ug902-vivado-high-level-synthesis.pdf

Vivado Design Suite User Guide High-Level Synthesis。 UG902 (v2018.3) December 20, 2018。 The Xilinx® Vivado® High-Level Synthesis (HLS) tool transforms a C specification into a register transfer level (RTL) implementation that you can synthesize into a Xilinx field programmable gate array (FPGA). You can write C specifications in C, C++, or SystemC, and the FPGA provides a massively parallel architecture with benefits in performance, cost, and power over traditional processors. This chapter provides an overview of high-level synthesis.