北航计算机组成实验Project4

上传者: u012774187 | 上传时间: 2019-12-21 18:55:54 | 文件大小: 776KB | 文件类型: zip
Project4 VerilogHDL完成单周期处理器开发 适合北航计算机系的学生 1.处理器应 MIPS-Lite3 指令集。 a) MIPS-Lite3={MIPS-Lite2,addi,addiu, slt,j,jal,jr}。 b) MIPS-Lite2 指令集:addu,subu,ori,lw,sw,beq,lui。 c) addi 可以不支持溢出。 2. 处理器为单周期设计。

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评论信息

  • sinat_26193859 :
    很适合学生使用
    2015-11-19
  • baidu_16051625 :
    modelsim上亲测可运行,适合初学者!
    2014-06-11

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