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阵列乘法器的设计与实现.rar

上传者： u012429555 | 上传时间： 2021-05-05 17:24:58 | 文件大小： 370KB | 文件类型： RAR
四位阵列乘法器的原理框图如图1.1所示，X=X1X2X3X4 Y=Y1Y2Y3Y4且X为被乘数的输入端，Y为乘数的输入端，M=M0M1M2M3M4M5M6M7为乘积的输出端。其基本原理是阵列的每一行送入乘数Y的每一位数位，而各行错开，形成的每一斜列则有被乘数X的每一位控制。 四位阵列乘法器的整体设计包含十六个加法器模块，虽然加法器数量多，但内部规则化，标准化程度高。加法器模块中由一个与门和一个全加器构成，由四个与门、两个异或门、一个三端接口的或门构成的全加器为底层设计。 顶层的四位阵列乘法器也采用原理图设计输入方式，在以十六个加法器为基础而构成的四位阵列乘法器，其主要以四个被乘数输入端、四个乘数输入端以及八个乘积输出端为主，外加还包括中间过程参与计算的进位输入端、部分积输入端和进位输出端、部分积输出端，这样一来就构成了一个完整的四位阵列乘法器。

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