CIC_Xilinx

[{"title":"（ 13 个子文件 11.58MB ） CIC_Xilinx","children":[{"title":"CIC","children":[{"title":"ECS.pdf <span style='color:#111;'> 421.53KB </span>","children":null,"spread":false},{"title":"Modelsim.pdf <span style='color:#111;'> 972.63KB </span>","children":null,"spread":false},{"title":"Configuration.pdf <span style='color:#111;'> 817.57KB </span>","children":null,"spread":false},{"title":"PACE.pdf <span style='color:#111;'> 537.81KB </span>","children":null,"spread":false},{"title":"FPGA concepts.pdf <span style='color:#111;'> 710.48KB </span>","children":null,"spread":false},{"title":"State CAD.pdf <span style='color:#111;'> 502.12KB </span>","children":null,"spread":false},{"title":"design flows.pdf <span style='color:#111;'> 1.34MB </span>","children":null,"spread":false},{"title":"synthesis.pdf <span style='color:#111;'> 636.08KB </span>","children":null,"spread":false},{"title":"Implementation.pdf <span style='color:#111;'> 440.56KB </span>","children":null,"spread":false},{"title":"Timing.pdf <span style='color:#111;'> 842.53KB </span>","children":null,"spread":false},{"title":"HDL synthesis.pdf <span style='color:#111;'> 1.00MB </span>","children":null,"spread":false},{"title":"Analyzing reports.pdf <span style='color:#111;'> 491.10KB </span>","children":null,"spread":false},{"title":"Architecture.pdf <span style='color:#111;'> 3.62MB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]