数电课设verilog做成数字钟
1、设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
2、整点报时。仿中央人民广播电台的整点报时信号，即从第59分50秒算起，每隔2秒钟发出一次信号，连续5次，最后一次信号结束即达到整点。不同步扣2分，可通过LED闪烁实现。
3、实现手动校时、校分、校秒功能。（缺一项扣一分，如果利用系统时钟校时，扣1分）
4、定时与闹钟功能，只需要设置分钟和小时。手动设置能在设定的时间发出闹铃声,声音用LED实现。
5、设计一个10个数的倒计时，闪烁显示，闪烁频率自定（无闪烁扣2分）。
6、用LCD液晶屏来显示当前时间。
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