Verilog语言控制ADS7844.rar

上传者: source03 | 上传时间: 2024-01-07 13:30:44 | 文件大小: 620KB | 文件类型: RAR
ADS7844共有三种工作模式,用verilog语言分别实现三种工作模式的主程序及仿真代码。在Quertus上编译成功,下载到FPGA中通过signalTap查看AD转换结果与实际电压值相符。

文件下载

资源详情

[{"title":"( 73 个子文件 620KB ) Verilog语言控制ADS7844.rar","children":[{"title":"Voltage","children":[{"title":"ADS7844B.v <span style='color:#111;'> 6.08KB </span>","children":null,"spread":false},{"title":"ADS7844A.v <span style='color:#111;'> 5.17KB </span>","children":null,"spread":false},{"title":"ADS7844.mpf <span style='color:#111;'> 101.60KB </span>","children":null,"spread":false},{"title":"ADS7844Atb.v <span style='color:#111;'> 4.46KB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"@_opt1","children":[{"title":"_lib2_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib3_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib2_0.qtl <span style='color:#111;'> 7.03KB </span>","children":null,"spread":false},{"title":"_lib4_0.qtl <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false},{"title":"_lib.qdb <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_lib4_0.qpg <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_lib4_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib2_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib3_0.qtl <span style='color:#111;'> 5.31KB </span>","children":null,"spread":false},{"title":"_lib1_0.qtl <span style='color:#111;'> 4.96KB </span>","children":null,"spread":false},{"title":"_lib3_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib1_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false}],"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"@_opt2","children":[{"title":"_lib2_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib3_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib5_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib2_0.qtl <span style='color:#111;'> 136.07KB </span>","children":null,"spread":false},{"title":"_lib4_0.qtl <span style='color:#111;'> 22.31KB </span>","children":null,"spread":false},{"title":"_lib6_0.qpg <span style='color:#111;'> 160.00KB </span>","children":null,"spread":false},{"title":"_lib7_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib7_0.qtl <span style='color:#111;'> 14.34KB </span>","children":null,"spread":false},{"title":"_lib5_0.qpg <span style='color:#111;'> 104.00KB </span>","children":null,"spread":false},{"title":"_lib.qdb <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_lib6_0.qtl <span style='color:#111;'> 19.05KB </span>","children":null,"spread":false},{"title":"_lib4_0.qpg <span style='color:#111;'> 160.00KB </span>","children":null,"spread":false},{"title":"_lib7_0.qpg <span style='color:#111;'> 104.00KB </span>","children":null,"spread":false},{"title":"_lib4_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib2_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib3_0.qtl <span style='color:#111;'> 101.18KB </span>","children":null,"spread":false},{"title":"_lib1_0.qtl <span style='color:#111;'> 80.69KB </span>","children":null,"spread":false},{"title":"_lib3_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib5_0.qtl <span style='color:#111;'> 14.77KB </span>","children":null,"spread":false},{"title":"_lib6_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false}],"spread":false},{"title":"_lib1_5.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib1_5.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib.qdb <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_temp","children":null,"spread":false},{"title":"_tempmsg","children":null,"spread":false},{"title":"@_opt","children":[{"title":"_lib2_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib3_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib5_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib2_0.qtl <span style='color:#111;'> 121.75KB </span>","children":null,"spread":false},{"title":"_lib4_0.qtl <span style='color:#111;'> 21.10KB </span>","children":null,"spread":false},{"title":"_lib6_0.qpg <span style='color:#111;'> 104.00KB </span>","children":null,"spread":false},{"title":"_lib7_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib7_0.qtl <span style='color:#111;'> 13.70KB </span>","children":null,"spread":false},{"title":"_lib5_0.qpg <span style='color:#111;'> 104.00KB </span>","children":null,"spread":false},{"title":"_lib.qdb <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_lib6_0.qtl <span style='color:#111;'> 15.15KB </span>","children":null,"spread":false},{"title":"_lib4_0.qpg <span style='color:#111;'> 152.00KB </span>","children":null,"spread":false},{"title":"_lib7_0.qpg <span style='color:#111;'> 104.00KB </span>","children":null,"spread":false},{"title":"_lib4_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib2_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib3_0.qtl <span style='color:#111;'> 94.79KB </span>","children":null,"spread":false},{"title":"_lib1_0.qtl <span style='color:#111;'> 83.08KB </span>","children":null,"spread":false},{"title":"_lib3_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_0.qpg <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"_lib5_0.qtl <span style='color:#111;'> 16.67KB </span>","children":null,"spread":false},{"title":"_lib6_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_0.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false}],"spread":false},{"title":"_lib1_5.qtl <span style='color:#111;'> 215.93KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 3.03KB </span>","children":null,"spread":false}],"spread":false},{"title":"ADS7844C.v <span style='color:#111;'> 5.47KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 56.00KB </span>","children":null,"spread":false},{"title":"ADS7844.cr.mti <span style='color:#111;'> 539B </span>","children":null,"spread":false},{"title":"ADS7844Btb.v <span style='color:#111;'> 5.22KB </span>","children":null,"spread":false},{"title":"verilog实现ADS7844控制.docx <span style='color:#111;'> 311.58KB </span>","children":null,"spread":false},{"title":"ADS7844Ctb.v <span style='color:#111;'> 5.05KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]

评论信息

免责申明

【只为小站】的资源来自网友分享,仅供学习研究,请务必在下载后24小时内给予删除,不得用于其他任何用途,否则后果自负。基于互联网的特殊性,【只为小站】 无法对用户传输的作品、信息、内容的权属或合法性、合规性、真实性、科学性、完整权、有效性等进行实质审查;无论 【只为小站】 经营者是否已进行审查,用户均应自行承担因其传输的作品、信息、内容而可能或已经产生的侵权或权属纠纷等法律责任。
本站所有资源不代表本站的观点或立场,基于网友分享,根据中国法律《信息网络传播权保护条例》第二十二条之规定,若资源存在侵权或相关问题请联系本站客服人员,zhiweidada#qq.com,请把#换成@,本站将给予最大的支持与配合,做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明